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Meyrem Kırman
Ph.D. Student, ECE
MS, Cornell
356 Upson Hall
Ithaca, NY 14853 USA
+1 (607) 255-3255
mkirman at csl.cornell.edu
I am working toward my Ph.D. with Prof. José Martínez. My research interests include checkpointed processor architectures, reconfigurable hardware, and hardware-software interaction.
I completed BS degrees in Computer Engineering and in Electronics Engineering in 2002 and 2003, respectively, both from Istanbul Technical University (ITU), and joined Cornell's MS/Ph.D. program in Fall 2003. I held a McMullen graduate fellowship during the 2003-04 academic year. Currently I am a recipient of Intel Research Foundation graduate fellowship.
Publications
A. Basu, N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Scavenger: A new last level cache architecture with global block priority. In Intl. Symp. on Microarchitecture (MICRO), Chicago, IL, Dec. 2007
E. İpek, M. Kırman, N. Kırman, and J.F. Martínez. Core Fusion: Accommodating software diversity in chip multiprocessors. In Intl. Symp. on Computer Architecture (ISCA), San Diego, CA, June 2007
Earlier version appears in Workshop on Complexity-effective Design, conc. with ISCA, Boston, MA, June 2006
N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in bus-based multicore design. In IEEE Micro Top Picks from Computer Architecture Conferences, Jan.-Feb., 2007 - Top Picks
N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In Intl. Symp. on Microachitecture (MICRO), Orlando, FL, Dec. 2006 - Best Paper Nomination
M. Kırman, N. Kırman, and J.F. Martínez. Correctly integrating checkpointed early resource recycling in chip multiprocessors. In Intl. Symp. on Microarchitecture (MICRO), Barcelona, Spain, Nov. 2005
N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Checkpointed early load retirement. In Intl. Symp. on High-Performance Computer Architecture (HPCA), San Francisco, CA, Feb. 2005 - Best Paper Award
Early version appears in Wksp. on Value Prediction and Value-based Optimization, conc. with ASPLOS, Oct. 2004
Professional Experience
- Intel Corporation, Architecture Research Lab, June-August 2006, Santa Clara, CA, USA
TA Duties
- Spring 2006 : ECE 572/CS 516 - Parallel Computer Architecture
- Fall 2005 : ECE 475/CS 416 - Computer Architecture
- Fall 2004 : ECE 475/CS 416 - Computer Architecture